Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAND2B1LPrimitive: Two input AND gate implemented in place of a Slice LatchIntroductionThis element allows the specification of a configurable Slice latch to take the function of a two input ANDgate with one input inverted (see Logic Table). The use of this element can reduce logic levels and increaselogic density of the part by trading off register/latch resources for logic. Xilinx suggests caution when usingthis component as it can affect register packing and density since specifying one or more AND2B1L or OR2Lcomponents in a Slice disallows the use of the remaining registers and latches.Logic TableInputsOutputsDI SRI O0 0 00 1 01 0 11 1 0Port DescriptionsPort Type Width FunctionO Output 1 Output of the AND gate.DI Input 1 Active high input that is generally connected to sourcing LUT locatedin the same Slice.SRI Input 1 Active low input that is generally source from outside of the Slice.Note To allow more than one AND2B1L or OR2B1L to be packed intoa single Slice, a common signal must be connected to this input.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs82 www.xilinx.com UG623 (v 11.4) December 2, 2009