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Xilinx Virtex-6 Libraries Guide for HDL Designs

Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design ElementsMUXF7_DPrimitive: 2-to-1 Look-Up Table Multiplexer with Dual OutputIntroductionThis design element provides a multiplexer function <strong>for</strong> use in creating a function-of-7 look-up table or a 16-to-1multiplexer in combination with the associated look-up tables. Local outputs (LO) of MUXF6 are connectedto the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0.When High, S selects I1.Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output connects toother inputs in the same CLB slice.Logic TableInputsOutputsS I0 I1 O LO0 I0 X I0 I01 X I1 I1 I1X 0 0 0 0X 1 1 1 1Port DescriptionsPort Direction Width FunctionO Output 1 Output of MUX to general routingLO Output 1 Output of MUX to local routingI0 Input 1 Input (tie to MUXF6 LO out)I1 Input 1 Input (tie to MUXF6 LO out)S Input 1 Input select to MUXDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNo<strong>Virtex</strong>-6 <strong>Libraries</strong> <strong>Guide</strong> <strong>for</strong> <strong>HDL</strong> <strong>Designs</strong>UG623 (v 11.4) December 2, 2009 www.xilinx.com 231

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