Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsBSCAN_VIRTEX6Primitive: Virtex®-6 JTAG Boundary-Scan Logic Access CircuitIntroductionThis design element allows access to and from internal logic by the JTAG Boundary Scan logic controller. Thisallows for communication between the internal running design and the dedicated JTAG pins of the FPGA.Each instance of this design element will handle one JTAG USER instruction (USER1 through USER4) as set withthe JTAG_CHAIN attribute. To handle all four USER instuctions, instantiate four of these elements and set theJTAG_CHAIN attribute appropriately.Note For specific information on boundary scan for an architecture, see the Programmable Logic Data Sheetfor this element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 83