Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design Elements);-- Control: 1-bit (each) Control Inputs/Status BitsOVERFLOW => OVERFLOW,-- 1-bit overflow in add/acc outputPATTERNBDETECT => PATTERNBDETECT, -- 1-bit active high pattern bar detect outputPATTERNDETECT => PATTERNDETECT, -- 1-bit active high pattern detect outputUNDERFLOW => UNDERFLOW,-- 1-bit active high underflow in add/acc output-- Data: 4-bit (each) Data PortsCARRYOUT => CARRYOUT,-- 4-bit carry outputP => P,-- 48-bit output-- Cascade: 30-bit (each) Cascade PortsACIN => ACIN,-- 30-bit A cascade data inputBCIN => BCIN,-- 18-bit B cascade inputCARRYCASCIN => CARRYCASCIN, -- 1-bit cascade carry inputMULTSIGNIN => MULTSIGNIN,-- 1-bit multiplier sign inputPCIN => PCIN,-- 48-bit P cascade input-- Control: 4-bit (each) Control Inputs/Status BitsALUMODE => ALUMODE,-- 4-bit ALU control inputCARRYINSEL => CARRYINSEL,-- 3-bit carry select inputCEINMODE => CEINMODE,-- 1-bit active high clock enable input for INMODE registersCLK => CLK,-- 1-bit Clock inputINMODE => INMODE,-- 5-bit INMODE control inputOPMODE => OPMODE,-- 7-bit operation mode inputRSTINMODE => RSTINMODE,-- 1-bit reset input for INMODE pipeline registers-- Data: 30-bit (each) Data PortsA => A,-- 30-bit A data inputB => B,-- 18-bit B data inputC => C,-- 48-bit C data inputCARRYIN => CARRYIN,-- 1-bit carry input signalD => D,-- 25-bit D data input-- Reset/Clock Enable: 1-bit (each) Reset/Clock Enable InputsCEA1 => CEA1,-- 1-bit active high clock enable input for 1st stage A registersCEA2 => CEA2,-- 1-bit active high clock enable input for 2nd stage A registersCEAD => CEAD,-- 1-bit active high clock enable input for pre-adder output registersCEALUMODE => CEALUMODE,-- 1-bit active high clock enable input for ALUMODE registersCEB1 => CEB1,-- 1-bit active high clock enable input for 1st stage B registersCEB2 => CEB2,-- 1-bit active high clock enable input for 2nd stage B registersCEC => CEC,-- 1-bit active high clock enable input for C registersCECARRYIN => CECARRYIN,-- 1-bit active high clock enable input for CARRYIN registerCECTRL => CECTRL,-- 1-bit active high clock enable input for OPMODE and carry registersCED => CED,-- 1-bit active high clock enable input for D registersCEM => CEM,-- 1-bit active high clock enable input for multiplier registersCEP => CEP,-- 1-bit active high clock enable input for P registersRSTA => RSTA,-- 1-bit reset input for A pipeline registersRSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit reset input for carry pipeline registersRSTALUMODE => RSTALUMODE,-- 1-bit reset input for ALUMODE pipeline registersRSTB => RSTB,-- 1-bit reset input for B pipeline registersRSTC => RSTC,-- 1-bit reset input for C pipeline registersRSTCTRL => RSTCTRL,-- 1-bit reset input for OPMODE pipeline registersRSTD => RSTD,-- 1-bit reset input for D pipeline registersRSTM => RSTM,-- 1-bit reset input for multiplier registersRSTP => RSTP-- 1-bit reset input for P pipeline registers-- End of DSP48E1_inst instantiationVerilog Instantiation Template// DSP48E1: 25x18 Two’s Complement Multiplier with Integrated 48-Bit, 3-Input Adder/Subtracter/Accumulator or 2-Input Logic Unit// Virtex-6// Xilinx HDL Language Template, version 11.1DSP48E1 #(.ACASCREG(1),// Number of pipeline registers between A/ACIN input and ACOUT output,// 0, 1, or 2.ADREG(1), // Number of pipeline registers on pre-adder output, 0 or 1.ALUMODEREG(1), // Number of pipeline registers on ALUMODE input, 0 or 1.AREG(1), // Number of pipeline registers on the A input, 0, 1 or 2.AUTORESET_PATDET("NO_RESET"),.A_INPUT("DIRECT"),.BCASCREG(1),// NO_RESET, RESET_MATCH, RESET_NOT_MATCH// Selects A input used, "DIRECT" (A port) or "CASCADE" (ACIN port)// Number of pipeline registers between B/BCIN input and BCOUT output,// 0, 1, or 2.BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2.B_INPUT("DIRECT"),// Selects B input used, "DIRECT" (B port) or "CASCADE" (BCIN port)Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 127