Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IBUF: Single-ended Input Buffer-- All devices-- Xilinx HDL Libraries Guide, version 11.2IBUF_inst : IBUFgeneric map (IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,-- "0"-"12" (Spartan-3E)-- "0"-"16" (Spartan-3A)IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,-- "AUTO", "0"-"6" (Spartan-3E)-- "AUTO", "0"-"8" (Spartan-3A)IOSTANDARD => "DEFAULT")port map (O => O, -- Buffer outputI => I -- Buffer input (connect directly to top-level port));-- End of IBUF_inst instantiationVerilog Instantiation Template// IBUF: Single-ended Input Buffer// All devices// Xilinx HDL Libraries Guide, version 11.2IBUF #(.IBUF_DELAY_VALUE("0"),// Specify the amount of added input delay for// the buffer: "0"-"12" (Spartan-3E)// "0"-"16" (Spartan-3A).IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input// register: "AUTO", "0"-"6" (Spartan-3E)// "AUTO", "0"-"8" (Spartan-3A).IOSTANDARD("DEFAULT") // Specify the input I/O standard)IBUF_inst (.O(O), // Buffer output.I(I) // Buffer input (connect directly to top-level port));// End of IBUF_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 153