Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosAvailable AttributesAttribute Type Allowed Values Default DescriptionWIDTH_A Integer 1 to 25 25 Controls the width of A input.WIDTH_B Integer 1 to 18 18 Controls the width of B input.LATENCY Integer 0, 1, 2, 3, 4 3 Number of pipeline registersDEVICE String “VIRTEX6”,“SPARTAN6”“VIRTEX6”• 1 - MREG == 1• 2 - AREG == BREG == 1 and MREG== 1 or MREG == 1 and PREG == 1• 3 - AREG == BREG == 1 and MREG== 1 and PREG == 1• 4 - AREG == BREG == 2 and MREG== 1 and PREG == 1Target hardware architecture.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- MULT_MACRO: Multiply Function implemented in a DSP48E-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2MULT_MACRO_inst : MULT_MACROgeneric map (DEVICE => "VIRTEX5", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"LATENCY => 3, -- Desired clock cycle latency, 0-4WIDTH_A => 18, -- Multiplier A-input bus width, 1-25WIDTH_B => 18) -- Multiplier B-input bus width, 1-18port map (P => P, -- Multiplier ouput bus, width determined by WIDTH_P genericA => A, -- Multiplier input A bus, width determined by WIDTH_A genericB => B, -- Multiplier input B bus, width determined by WIDTH_B genericCE => CE, -- 1-bit active high input clock enableCLK => CLK, -- 1-bit positive edge clock inputRST => RST -- 1-bit input active high reset);-- End of MULT_MACRO_inst instantiationVerilog Instantiation Template// MULT_MACRO: Multiply Function implemented in a DSP48E// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2MULT_MACRO #(.DEVICE("VIRTEX5"), // Target Device: ""VIRTEX5", "VIRTEX6", "SPARTAN6".LATENCY(3), // Desired clock cycle latency, 0-4.WIDTH_A(18), // Multiplier A-input bus width, 1-25.WIDTH_B(18), // Multiplier B-input bus width, 1-18) MULT_MACRO (.P(P), // Multiplier output bus, width determined by WIDTH_P parameter.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter.CE(CE), // 1-bit active high input clock enable.CLK(CLK), // 1-bit positive edge clock input.RST(RST) // 1-bit input active high reset);Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 73