Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsCLKOUT2_PHASE => 0.0,CLKOUT2_USE_FINE_PS => FALSE,CLKOUT3_DIVIDE => 1,CLKOUT3_DUTY_CYCLE => 0.5,CLKOUT3_PHASE => 0.0,CLKOUT3_USE_FINE_PS => FALSE,CLKOUT4_CASCADE => FALSE,CLKOUT4_DIVIDE => 1,CLKOUT4_DUTY_CYCLE => 0.5,CLKOUT4_PHASE => 0.0,CLKOUT4_USE_FINE_PS => FALSE,CLKOUT5_DIVIDE => 1,CLKOUT5_DUTY_CYCLE => 0.5,CLKOUT5_PHASE => 0.0,CLKOUT5_USE_FINE_PS => FALSE,CLKOUT6_DIVIDE => 1,CLKOUT6_DUTY_CYCLE => 0.5,CLKOUT6_PHASE => 0.0,CLKOUT6_USE_FINE_PS => FALSE,CLOCK_HOLD => FALSE,COMPENSATION => "ZHOLD",DIVCLK_DIVIDE => 1,REF_JITTER1 => 0.0,REF_JITTER2 => 0.0,-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Counter divide value-- Counter output duty cycle-- Counter output phase relative to the output clock-- Counter fine variable phase shift enable.-- Defines how the PLL feedback is configured. SYSTEM_SYNCHRONOUS-- indicates the MMCM is configured to provide a negative hold time-- SOURCE_SYNCHRONOUS indicates the MMCM is configured to provide a zero-- hold time SYSTEM_SYNCHRONOUS also does the AUTO detect of the-- feedback and it indicates the MMCM is configured based on how a-- customer has connected it. This can be any of the following: INTERNAL-- indicates the MMCM is using its own internal feedback path so no-- delay is being compensated. EXTERNAL indicates a network external to-- the FPGA is being compensated. HROWCLK indicates the path between the-- MMCM and the HROWCLK is being compensated CASCADE indicates cascading-- of 2 MMCM’s.-- Counter divide value, always configured for 50% duty cycle-- The reference clock2 jitter is specified in terms of the UI which is-- a percentage of the reference clock. The number provided should be-- the maximum peak to peak value our part can expect on the input-- clock. Default is 0.1UI. This parameter should support out to three-- decimal places.-- The reference clock1 jitter is specified in terms of the UI which is-- a percentage of the reference clock. The number provided should be-- the maximum peak to peak value our part can expect on the input-- clock. Default is 0.1UI. This parameter should support out to three-- decimal places.-- When TRUE, the MMCM locks before DONE goes highSTARTUP_WAIT => FALSE)port map (CLKFBOUT => CLKFBOUT,-- 1-bit MMCM Feedback clock outputCLKFBOUTB => CLKFBOUTB, -- 1-bit Inverted MMCM feedback clock outputCLKFBSTOPPED => CLKFBSTOPPED, -- 1-bit Status pin indicating that the feedback clock has stopped.CLKINSTOPPED => CLKINSTOPPED, -- 1-bit Status pin indicating that the input clock has stoppedCLKOUT0 => CLKOUT0, -- 1-bit MMCM clock output 0CLKOUT0B => CLKOUT0B, -- 1-bit Inverted MMCM clock output 0CLKOUT1 => CLKOUT1, -- 1-bit MMCM clock output 1CLKOUT1B => CLKOUT1B, -- 1-bit Inverted MMCM clock output 1CLKOUT2 => CLKOUT2, -- 1-bit MMCM clock output 2CLKOUT2B => CLKOUT2B, -- 1-bit Inverted MMCM clock output 2CLKOUT3 => CLKOUT3, -- 1-bit MMCM clock output 3CLKOUT3B => CLKOUT3B, -- 1-bit Inverted MMCM clock output 3CLKOUT4 => CLKOUT4, -- 1-bit MMCM clock output 4CLKOUT5 => CLKOUT5,CLKOUT6 => CLKOUT6,DO => DO,DRDY => DRDY,LOCKED => LOCKED,PSDONE => PSDONE,CLKFBIN => CLKFBIN,CLKIN1 => CLKIN1,CLKIN2 => CLKIN2,CLKINSEL => CLKINSEL,DADDR => DADDR,DCLK => DCLK,DEN => DEN,DI => DI,DWE => DWE,-- 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer-- 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer-- 16-bit DRP output signals-- 1-bit DRP ready signal-- 1-bit MMC locked signal-- 1-bit Phase shift done-- 1-bit Feedback clock pin to the MMCM-- 1-bit Reference clock pin 1 to the MMCM-- 1-bit Reference clock pin 2 to the MMCM-- 1-bit Clock select control pin to the MMCM; 1 = CLKIN1; 0=CLKIN2-- 7-bit DRP address control signals-- 1-bit DRP clock signal (connects to interconnect clock)-- 1-bit DRP enable signal-- 16-bit DRP data inputs-- 1-bit DRP write enableVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 221