Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- CAPTURE_VIRTEX6: Virtex-6 Readback Register Capture Control-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2CAPTURE_VIRTEX6_inst : CAPTURE_VIRTEX6generic map (ONESHOT => TRUE -- Specifies the procedure for performing single readback per CAP trigger.)port map (CAP => CAP, -- 1-bit Readback capture triggerCLK => CLK -- 1-bit Readback capture clock);-- End of CAPTURE_VIRTEX6_inst instantiationVerilog Instantiation Template// CAPTURE_VIRTEX6: Virtex-6 Readback Register Capture Control// Virtex-6// Xilinx HDL Language Template, version 11.1CAPTURE_VIRTEX6 #(.ONESHOT("TRUE") // Specifies the procedure for performing single readback per CAP trigger.)CAPTURE_VIRTEX6_inst (.CAP(CAP), // 1-bit Readback capture trigger.CLK(CLK) // 1-bit Readback capture clock);// End of CAPTURE_VIRTEX6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 111