Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsODDRPrimitive: Dedicated Dual Data Rate (DDR) Output RegisterIntroductionThis design element is a dedicated output register for use in transmitting dual data rate (DDR) signals fromFPGA devices. The ODDR primitive’s interface with the FPGA fabric are not limited to opposite edges. TheODDR is available with modes that allow data to be presented from the FPGA fabric at the same clock edge. Thisfeature allows designers to avoid additional timing complexities and CLB usage. In addition, the ODDR worksin conjunction with SelectIO features.ODDR ModesThis element has two modes of operation. These modes are set by the DDR_CLK_EDGE attribute.• OPPOSITE_EDGE mode - The data transmit interface uses the classic DDR methodology. Given a data andclock at pin D1-2 and C respectively, D1 is sampled at every positive edge of clock C, and D2 is sampled atevery negative edge of clock C. Q changes every clock edge.• SAME_EDGE mode - Data is still transmitted at the output of the ODDR by opposite edges of clock C.However, the two inputs to the ODDR are clocked with a positive clock edge of clock signal C and an extraregister is clocked with a negative clock edge of clock signal C. Using this feature, DDR data can now bepresented into the ODDR at the same clock edge.Port DescriptionsPort Type Width FunctionQ Output 1 Data Output (DDR) - The ODDR output that connects to the IOBpad.C Input 1 Clock Input - The C pin represents the clock input pin.CE Input 1 Clock Enable Input - When asserted High, this port enables theclock input on port C.D1 : D2 Input 1 (each) Data Input - This pin is where the DDR data is presented intothe ODDR module.R Input 1 Reset - Depends on how SRTYPE is set.S Input 1 Set - Active High asynchronous set pin. This pin can also beSynchronous depending on the SRTYPE attribute.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 247