Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsDDR3_DATA => 1,-- For DDR3, if the I/O is a DQ or DQS pin, set to 1. If control, address,-- clock, etc. set to 0.INIT_OQ => "0",-- Defines the initial value of OQ output.INIT_TQ => "0",-- Defines the initial value of TQ output.INTERFACE_TYPE => "DEFAULT", -- To bypass DDR3 circuitryODELAY_USED => 0,-- BUFO drives IODELAY for write leveling or BUFO alignment.SERDES_MODE => "MASTER", -- Defines whether the OSERDES module is a master or slave when width-- expansion is used.SRVAL_OQ => "0",-- Defines the value of OQ output when reset is invoked.SRVAL_TQ => "0",-- Defines the value of TQ output when reset is invoked.TRISTATE_WIDTH => 4-- If DATA_RATE_TQ = DDR, DATA_WIDTH = 4, and DATA_RATE_OQ = DDR, value is-- limited to 1 or 4. For all other settings of DATA_RATE_TQ, DATA_WIDTH,-- and DATA_RATE_OQ, value is limited to 1.)port map (OCBEXTEND => OCBEXTEND,OFB => OFB,-- 1-bit Feedback path for Data OutputOQ => OQ,-- 1-bit Data Path Output-- SHIFTOUT1/SHIFTOUT2: 1-bit (each) Carry Out for data input expansion. Connect to SHIFTIN1/2 ofmaster.SHIFTOUT1 => SHIFTOUT1,SHIFTOUT2 => SHIFTOUT2,TFB => TFB,);TQ => TQ,CLK => CLK,-- 1-bit 3-State Path Output-- 1-bit High Speed Clock Input - This clock input is used to drive the-- parallel-to-serial converters. The possible source for the CLK port is-- from one of the following clock resources: - Ten global clock lines in a-- clock region - Four regional clock lines - Four clock capable I/Os-- (within adjacent clock region) - Fabric (through bypass).CLKDIV => CLKDIV,-- 1-bit Divided High Speed Clock InputCLKPERF => CLKPERF,-- 1-bit Input for performance path from PLL.CLKPERFDELAY => CLKPERFDELAY, -- 1-bit Delayed version of BUFO from IODELAY-- D1 - D6: 1-bit (each) 1-bit parallel Data InputD1 => D1,D2 => D2,D3 => D3,D4 => D4,D5 => D5,D6 => D6,OCE => OCE,-- 1-bit Parallel to serial converter (data) clock enableODV => ODV,-- 1-bit Used for DDR3. Set to 1 if the ODELAY values exceeds 180 degrees-- of the clock period.RST => RST,-- SHIFTIN1/SHIFTIN2: 1-bit (each) 1-bit Data Input ExpansionSHIFTIN1 => SHIFTIN1,SHIFTIN2 => SHIFTIN2,-- T1 - T4: 1-bit (each) Parallel 3-State InputsT1 => T1,T2 => T2,T3 => T3,T4 => T4,TCE => TCE,WC => WC-- End of OSERDESE1_inst instantiation-- 1-bit Parallel to serial converter (3-state) clock enable-- 1-bit Used for DDR3. Resets FIFO counters and turns IODELAY from IDELAY-- to ODELAY.Verilog Instantiation Template// OSERDESE1: Dedicated IOB Output Serializer// Virtex-6// Xilinx HDL Language Template, version 11.1OSERDESE1 #(.DATA_RATE_OQ("DDR"),.DATA_RATE_TQ("DDR"),// Defines whether the data changes at every clock edge or every positive// clock edge with respect to CLK.// Defines whether the 3-state changes at every clock edge, every positive// clock edge, or buffer configuration with respect to CLK.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 253