Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- CFGLUT5: Reconfigurable 5-input LUT-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2CFGLUT5_inst : CFGLUT5generic map (INT => X"00000000")port map (CDO => CDO, -- Reconfiguration cascade outputO5 => O5, -- 4-LUT outputO6 => O6, -- 5-LUT outputCDI => CDI, -- Reconfiguration data inputCE => CE, -- Reconfiguration enable inputCLK => CLK, -- Clock inputI0 => I0, -- Logic data inputI1 => I1, -- Logic data inputI2 => I2, -- Logic data inputI3 => I3, -- Logic data inputI4 => I4 -- Logic data input);-- End of CFGLUT5_inst instantiationVerilog Instantiation Template// CFGLUT5: Reconfigurable 5-input LUT// Virtex-5, Virext-5, Spartan-6// Xilinx HDL Libraries Guide, version 11.2CFGLUT5 #(.INIT(32’h00000000) // Specify initial LUT contents) CFGLUT5_inst (.CDO(CDO), // Reconfiguration cascade output.O5(O5), // 4-LUT output.O6(O6), // 5-LUT output.CDI(CDI), // Reconfiguration data input.CE(CE), // Reconfiguration enable input.CLK(CLK), // Clock input.I0(I0), // Logic data input.I1(I1), // Logic data input.I2(I2), // Logic data input.I3(I3), // Logic data input.I4(I4) // Logic data input);// End of CFGLUT5_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs116 www.xilinx.com UG623 (v 11.4) December 2, 2009