Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 64-Bit Value All zeros Specifies the logic value for thelook-up tables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT6: 6-input Look-Up Table with general output-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT6_inst : LUT6generic map (INIT => X"0000000000000000") -- Specify LUT Contentsport map (O => O, -- LUT general outputI0 => I0, -- LUT inputI1 => I1, -- LUT inputI2 => I2, -- LUT inputI3 => I3, -- LUT inputI4 => I4, -- LUT inputI5 => I5 -- LUT input);-- End of LUT6_inst instantiationVerilog Instantiation Template// LUT6: 6-input Look-Up Table with general output// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT6 #(.INIT(64’h0000000000000000) // Specify LUT Contents) LUT6_inst (.O(O), // LUT general output.I0(I0), // LUT input.I1(I1), // LUT input.I2(I2), // LUT input.I3(I3), // LUT input.I4(I4), // LUT input.I5(I5) // LUT input);// End of LUT6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs216 www.xilinx.com UG623 (v 11.4) December 2, 2009