Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFHCE: Clock buffer for a single clocking region with clock enable// Virtex-6// Xilinx HDL Language Template, version 11.4BUFHCE #(.INIT_OUT(0) // Initial output value, also indicates stop low vs stop high behavior)BUFHCE_inst (.O(O), // 1-bit The output of the BUFH.CE(CE), // 1-bit Enables propagation of signal from I to O. When low, sets output to 0..I(I) // 1-bit The input to the BUFH);// End of BUFHCE_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 103