Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- CARRY4: Fast Carry Logic Component-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2CARRY4_inst : CARRY4port map (CO => CO,-- 4-bit carry outO => O,-- 4-bit carry chain XOR data outCI => CI,-- 1-bit carry cascade inputCYINIT => CYINIT, -- 1-bit carry initializationDI => DI,-- 4-bit carry-MUX data inS => S-- 4-bit carry-MUX select input);-- End of CARRY4_inst instantiationVerilog Instantiation Template// CARRY4: Fast Carry Logic Component// Virtex-5, Virext-5, Spartan-6// Xilinx HDL Libraries Guide, version 11.2CARRY4 CARRY4_inst (.CO(CO),// 4-bit carry out.O(O),// 4-bit carry chain XOR data out.CI(CI),// 1-bit carry cascade input.CYINIT(CYINIT), // 1-bit carry initialization.DI(DI),// 4-bit carry-MUX data in.S(S)// 4-bit carry-MUX select input);// End of CARRY4_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 113