Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPULLDOWNPrimitive: Resistor to GND for Input Pads, Open-Drain, and 3-State OutputsIntroductionThis resistor element is connected to input, output, or bidirectional pads to guarantee a logic Low level fornodes that might float.Port DescriptionsPort Direction Width FunctionO Output 1 Pulldown output (connect directly to top level port)Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- PULLDOWN: I/O Buffer Weak Pull-down-- All FPGA-- Xilinx HDL Libraries Guide, version 11.2PULLDOWN_inst : PULLDOWNport map (O => O -- Pulldown output (connect directly to top-level port));-- End of PULLDOWN_inst instantiationVerilog Instantiation Template// PULLDOWN: I/O Buffer Weak Pull-down// All FPGA// Xilinx HDL Libraries Guide, version 11.2PULLDOWN PULLDOWN_inst (.O(O) // Pulldown output (connect directly to top-level port));// End of PULLDOWN_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 257