Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionDEVICE String “VIRTEX6”,“SPARTAN6”“VIRTEX6”Target hardware architecture.LATENCY Integer 0, 1, 2 2 Number of pipeline registers.• 1 - PREG == 1• 2 - AREG == BREG == CREG ==PREGWIDTH Integer 1-48 48 A, B, and RESULT port width; internalcustomers can override B and RESULTport widths using other parametersWIDTH_B Integer 1-48 48 Port B width override.WIDTH_RESULT Integer 1-48 48 Result port width override.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- ADDSUB_MACRO: Variable width & latency - Adder / Subtrator implemented in a DSP48E-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2ADDSUB_MACRO_inst : ADDSUB_MACROgeneric map (DEVICE => "VIRTEX5", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"LATENCY => 2, -- Desired clock cycle latency, 0-2WIDTH => 48) -- Input / Output bus width, 1-48port map (CARRYOUT => CARRYOUT, -- 1-bit carry-out output signalRESULT => RESULT, -- Add/sub result output, width defined by WIDTH genericA => A,-- Input A bus, width defined by WIDTH genericADD_SUB => ADD_SUB, -- 1-bit add/sub input, high selects add, low selects subtractB => B,-- Input B bus, width defined by WIDTH genericCARRYIN => CARRYIN, -- 1-bit carry-in inputCE => CE,-- 1-bit clock enable inputCLK =>CLK,-- 1-bit clock inputRST => RST-- 1-bit active high synchronous reset);-- End of ADDSUB_MACRO_inst instantiationVirtex-6 Libraries Guide for HDL Designs58 www.xilinx.com UG623 (v 11.4) December 2, 2009