Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsFDCEPrimitive: D Flip-Flop with Clock Enable and Asynchronous ClearIntroductionThis design element is a single D-type flip-flop with clock enable and asynchronous clear. When clock enable(CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of this design element istransferred to the corresponding data output (Q) during the Low-to-High clock (C) transition. When CLR is High,it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored.This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsCLR CE D C Q1 X X X 00 0 X X No Change0 1 D ↑ DDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Binary 0 0 Sets the initial value of Q output after configuration.For Spartan®-6 devices, the INIT value shouldalways match the polarity of the set or reset. In thecase of FDCE, the INIT should be 0. If set to 1, anasynchronous circuit must be created to exhibit thisbehavior, which Xilinx does not recommend.Virtex-6 Libraries Guide for HDL Designs132 www.xilinx.com UG623 (v 11.4) December 2, 2009