Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsFIFO36E1Primitive: 36 kb FIFO (First In, First Out) Block RAM MemoryIntroductionVirtex®-6 devices contain several block RAM memories that can be configured as FIFOs, automaticerror-correction RAM, or general-purpose 36 kb or 18 kb RAM/ROM memories. These block RAM memoriesoffer fast and flexible storage of large amounts of on-chip data. The FIFO36E1 allows access to the block RAM inthe 36 kb FIFO configurations. This component can be configured and used as a 4-bit wide by 8K deep, 9-bitby 4K deep, 18-bit by 2K deep, 36-bit wide by 1K deep, or 72-bit wide by 512 deep synchronous or dual-clock(asynchronous) FIFO RAM with all associated FIFO flags.When using the dual-clock mode with independent clocks, depending on the offset between read and write clockedges, the Empty, Almost Empty, Full, and Almost Full flags can deassert one cycle later. Due to the asynchronousnature of the clocks, the simulation model only reflects the deassertion latency cycles listed in the User Guide.Note For a 72-bit wide by 512 deep FIFO, the FIFO36_72 mode must be used. For smaller configurations of theFIFO, the FIFO18E1 can be used. If error-correction circuitry is desired, the FIFO36_72 mode must be used.Port DescriptionsPort Type Width FunctionALMOSTEMPTY Output 1 Programmable flag to indicate the FIFO is almost empty.ALMOST_EMPTY_OFFSET attribute specifies where totrigger this flag.ALMOSTFULL Output 1 Programmable flag to indicate the FIFO is almost full.ALMOST_FULL_OFFSET attribute specifies where totrigger this flag.DBITERR Output 1 Status output from ECC function to indicate a double biterror was detected. EN_ECC_READ needs to be TRUE inorder to use this functionality.DI[63:0] Input 64 FIFO data input bus.DIP[7:0] Input 8 FIFO parity data input bus.DO[63:0] Output 64 FIFO data output bus.DOP[7:0] Output 8 FIFO parity data output bus.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 141