Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosName Direction Width FunctionDIB Input See Configuration Tablebelow.ADDRA, ADDRB Input See Configuration Tablebelow.WEA, WEB Input See Configuration Tablebelow.Data input bus addressed by ADDRB.Address input buses for Port A, B.Write enable for Port A, B.ENA, ENB Input 1 Write/Read enables for Port A, B.RSTA, RSTB Input 1 Output registers synchronous reset for Port A, B.REGCEA, REGCEB Input 1 Output register clock enable input for Port A, B (validonly when DO_REG=1)CLKA, CLKB Input 1 Write/Read clock input for Port A, B.Configuration TableWRITE_WIDTH_A/B-DIA/DIB36 - 1918 - 109 - 54 - 3READ_WIDTH_A/B-DOA/DOB BRAM_SIZE ADDRA/B WEA/B36 - 19 36Kb1018-10 119 - 5 124 - 3 132 14136 - 19 36Kb1118-10 119 - 5 124 - 3 132 14136-19 36Kb1218-10 129 - 5 124 - 3 132 14136-19 36Kb1318-10 139 - 5 134 - 3 132 141151515154211Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 37