Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort Type Width Functionautomatically locks after power on. No extra reset is required.LOCKED will be deasserted if the input clock stops or the phasealignment is violated (e.g., input clock phase shift). The MMCMautomatically reacquires lock after LOCKED is deasserted.PWRDWN Input 1 Powers down instantiated but unused MMCMs.RST Input 1 Asynchronous reset signal. The RST signal is an asynchronousreset for the MMCM. The MMCM will synchronously re-enableitself when this signal is released (i.e., MMCM re-enabled). Areset is not required when the input clock conditions change (e.g.,frequency).Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoRecommendedNoAvailable AttributesAttribute Type Allowed Values Default DescriptionBANDWIDTH String “OPTIMIZED”,“HIGH”,“LOW”CLKFBOUT_MULT_FCLKFBOUT_PHASE3 significantdigit Float3 significantdigit Float1.000 to64.000-360.000 to360.000CLKIN1_PERIOD Float (nS) 1.000 to1000.000CLKOUT0_DIVIDE_FCLKOUT[0:6]_DUTY_CYCLE3 significantdigit Float3 significantdigit Float1.000 to128.0000.001 to0.999“OPTIMIZED” Specifies the MMCM programmingalgorithm affecting the jitter, phase margin,and other characteristics of the MMCM.1.000 Specifies the amount to multiplyall CLKOUT clock outputs if adifferent frequency is desired. Thisnumber, in combination with theassociated CLKOUT#_DIVIDE value andDIVCLK_DIVIDE value, will determine theoutput frequency.0.000 Specifies the phase offset in degrees ofthe clock feedback output. Shifting thefeedback clock results in a negative phaseshift of all output clocks to the MMCM.0.000 Specifies the input period in ns to theMMCM CLKIN1 input. Resolution is downto the ps. This information is mandatoryand must be supplied.1.000 Specifies the amount to divide theassociated CLKOUT clock output if adifferent frequency is desired. This numberin combination with the CLKFBOUT_MULTand DIVCLK_DIVIDE values will determinethe output frequency.0.500 Specifies the Duty Cycle of the associatedCLKOUT clock output in percentage (i.e.,0.50 will generate a 50% duty cycle).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 225