Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsIBUFPrimitive: Input BufferIntroductionThis design element is automatically inserted (inferred) by the synthesis tool to any signal directly connectedto a top-level input or in-out port of the design. You should generally let the synthesis tool infer this buffer.However, it can be instantiated into the design if required. In order to do so, connect the input port (I) directly tothe associated top-level input or in-out port, and connect the output port (O) to the logic sourced by that port.Modify any necessary generic maps (VHDL) or named parameter value assignment (Verilog) in order to changethe default behavior of the component.Port DescriptionsPort Direction Width FunctionO Output 1 Buffer outputI Input 1 Buffer inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoIn general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code. However, if desired, they be manually instantiated byeither copying the instantiation code from the appropriate Libraries Guide HDL template and pasting it into thetop-level entity/module of your code. It is recommended to always put all I/O components on the top-level of thedesign to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of thedesign and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.Available AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL Designs152 www.xilinx.com UG623 (v 11.4) December 2, 2009