Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionDATA_RATE_OQ String “DDR”, “SDR” “DDR” Defines whether the data changes at every clockedge or every positive clock edge with respectto CLK.DATA_RATE_TQ String “DDR”,“BUF”,“SDR”“DDR”Defines whether the 3-state changes at everyclock edge, every positive clock edge, or bufferconfiguration with respect to CLK.DATA_WIDTH Integer 4, 2, 3, 5, 6, 7, 8, 10 4 • If DATA_RATE_OQ = DDR, value is limitedto 4, 6, 8, or 10.• If DATA_RATE_OQ = SDR, value is limitedto 2, 3, 4, 5, 6, 7, or 8.DDR3_DATA Integer 1, 0 1 For DDR3, if the I/O is a DQ or DQS pin, set to 1.If control, address, clock, etc. set to 0.INIT_OQ Binary 1’b0 to 1’b1 1’b0 Defines the initial value of OQ output.INIT_TQ Binary 1’b0 to 1’b1 1’b0 Defines the initial value of TQ output.INTERFACE_TYPE String “DEFAULT”,“MEMORY_DDR3”“DEFAULT”To bypass DDR3 circuitry.ODELAY_USED Integer 0, 1 0 BUFO drives IODELAY for write leveling orBUFO alignment.SERDES_MODE String “MASTER”,“SLAVE”“MASTER”Defines whether the OSERDES module is amaster or slave when width expansion is used.SRVAL_OQ Binary 1’b0 to 1’b1 1’b0 Defines the value of OQ output when reset isinvoked.SRVAL_TQ Binary 1’b0 to 1’b1 1’b0 Defines the value of TQ output when reset isinvoked.TRISTATE_WIDTH Integer 4, 1 4 If DATA_RATE_TQ = DDR, DATA_WIDTH = 4,and DATA_RATE_OQ = DDR, value is limited to1 or 4. For all other settings of DATA_RATE_TQ,DATA_WIDTH, and DATA_RATE_OQ, value islimited to 1.VHDL Instantiation Template-- OSERDESE1: Dedicated IOB Output Serializer-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2OSERDESE1_inst : OSERDESE1generic map (DATA_RATE_OQ => "DDR",DATA_RATE_TQ => "DDR",DATA_WIDTH => 4,-- Defines whether the data changes at every clock edge or every positive-- clock edge with respect to CLK.-- Defines whether the 3-state changes at every clock edge, every positive-- clock edge, or buffer configuration with respect to CLK.-- If DATA_RATE_OQ = DDR, value is limited to 4, 6, 8, or 10. If-- DATA_RATE_OQ = SDR, value is limited to 2, 3, 4, 5, 6, 7, or 8.Virtex-6 Libraries Guide for HDL Designs252 www.xilinx.com UG623 (v 11.4) December 2, 2009