Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsOBUFTDSPrimitive: 3-State Output Buffer with Differential Signaling, Active-Low Output EnableIntroductionThis design element is an output buffer that supports low-voltage, differential signaling. For the OBUFTDS,a design level interface signal is represented as two distinct ports (O and OB), one deemed the "master" andthe other the "slave." The master and the slave are opposite phases of the same logical signal (for example,MYNET_P and MYNET_N).Logic TableInputsOutputsI T O OBX 1 Z Z0 0 0 11 0 1 0Port DescriptionsPort Direction Width FunctionO Output 1 Diff_p output (connect directly to top level port)OB Output 1 Diff_n output (connect directly to top level port)I Input 1 Buffer inputT Input 1 3-state enable inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 245