Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFG: Global Clock Buffer (source by an internal signal)// All FPGAs// Xilinx HDL Libraries Guide, version 11.2BUFG BUFG_inst (.O(O), // Clock buffer output.I(I) // Clock buffer input);// End of BUFG_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 87