Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.InstantiationInferenceCORE Generator and wizardsMacro supportAvailable AttributesYesNoNoRecommendedAttribute Type Allowed Values Default DescriptionWIDTH_PREADD Integer 1 to 24 24 Controls the width of PREADD1and PREADD2 inputs.WIDTH_MULTIPLIER Integer 1 to 18 18 Controls the width of MULTIPLIERinput.WIDTH_PRODUCT Integer 1 to 48 48 Controls the width of MULTIPLIERoutput.LATENCY Integer 0, 1, 2, 3, 4 3 Number of pipeline registersDEVICE String “VIRTEX6”,“SPARTAN6”“VIRTEX6”• 1 - MREG == 1• 2 - AREG == BREG == 1 andMREG == 1 or MREG == 1 andPREG == 1• 3 - AREG == BREG == 1 andMREG == 1 and PREG == 1• 4 - AREG == BREG == 2 andMREG == 1 and PREG == 1Target hardware architecture.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- ADDMACC_MACRO: Add and Multiple Accumulate Function implemented in a DSP48E-- Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2ADDMACC_MACRO_inst : ADDMACC_MACROgeneric map (DEVICE => "VIRTEX6", -- Target Device: "VIRTEX6", "SPARTAN6"LATENCY => 3, -- Desired clock cycle latency, 1-4WIDTH_PREADD => 18, -- Pre-Adder input bus width, 1-25WIDTH_MULTIPLIER => 18, -- Multiplier input bus width, 1-18WIDTH_PRODUCT => 48) -- Product output bus width, 1-48port map (PRODUCT => PRODUCT, -- ADDMACC ouput bus, width determined by WIDTH_PRODUCT genericMULTIPLIER => MULTIPLIER, -- MULTIPLIER input bus, width determined by WIDTH_MULTIPLIER genericPREADDER1 => PREADDER1, -- 1st Pre-Adder input bus, width determined by WIDTH_PREADDER genericPREADDER2 => PREADDER2, -- 2nd Pre-Adder input bus, width determined by WIDTH_PREADDER genericCARRYIN => CARRYIN, -- 1-bit carry-in input to accumulatorCE => CE, -- 1-bit active high input clock enableCLK => CLK, -- 1-bit positive edge clock inputLOAD => LOAD, -- 1-bit active high input load accumulator enableLOAD_DATA => LOAD_DATA, -- Load accumulator input data,Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 55