Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionUSE_MULT String “MULTIPLY”,“DYNAMIC”,“NONE”USE_PATTERN_DETECTString“NO_PATDET”,“PATDET”USE_SIMD String “ONE48”,“FOUR12”,“TWO24”“MULTIPLY”Selects usage of the Multiplier. Set to NONE tosave power when using only the adder/LogicUnit. The DYNAMIC setting indicates thatthe user is switching between A*B and A:Boperations on the fly and therefore needs to getthe worst case timing of the two paths.“NO_PATDET” Set to PATDET to enable pattern detection in thesimulation model and speed files.“ONE48”Selects usage of the SIMD (Single InstructionMultiple Data) adder/Logic Unit. Selects betweenone 48-bit Logic Unit, two 24-bit Logic Units,or four 12-bit Logic Units. Note that all four12 bit Logic Units share the same Instruction(i.e. all can subtract on the same cycle or addon the same cycle). This allows the 48 bit adderto be broken up into smaller adders for lesscomputationally intensive applications. SIMDonly has an effect on arithmetic operation (add,accumulate, subtract, etc.) and has no effect onlogical operations.VHDL Instantiation Template-- DSP48E1: 25x18 Two’s Complement Multiplier with Integrated 48-Bit, 3-Input Adder/Subtracter/Accumulator or 2-Input Logic Unit-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2DSP48E1_inst : DSP48E1generic map (ACASCREG => 1,-- Number of pipeline registers between A/ACIN input and ACOUT output,-- 0, 1, or 2ADREG => 1, -- Number of pipeline registers on pre-adder output, 0 or 1ALUMODEREG => 1, -- Number of pipeline registers on ALUMODE input, 0 or 1AREG => 1, -- Number of pipeline registers on the A input, 0, 1 or 2AUTORESET_PATDET => "NO_RESET", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCHA_INPUT => "DIRECT",-- Selects A input used, "DIRECT" (A port) or "CASCADE" (ACIN port)BCASCREG => 1,-- Number of pipeline registers between B/BCIN input and BCOUT output,-- 0, 1, or 2BREG => 1, -- Number of pipeline registers on the B input, 0, 1 or 2B_INPUT => "DIRECT",-- Selects B input used, "DIRECT" (B port) or "CASCADE" (BCIN port)CARRYINREG => 1, -- Number of pipeline registers for the CARRYIN input, 0 or 1CARRYINSELREG => 1, -- Number of pipeline registers for the CARRYINSEL input, 0 or 1CREG => 1, -- Number of pipeline registers on the C input, 0 or 1DREG => 1, -- Number of pipeline registers on the D input, 0 or 1INMODEREG => 1, -- Number of pipeline registers on INMODE input, 0 or 1MASK => X"3fffffffffff",-- 48-bit Mask value for pattern detectMREG => 1, -- Number of multiplier pipeline registers, 0 or 1OPMODEREG => 1, -- Number of pipeline registers on OPMODE input, 0 or 1PATTERN => X"000000000000", -- 48-bit Pattern match for pattern detectPREG => 1, -- Number of pipeline registers on the P output, 0 or 1SEL_MASK => "MASK",-- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"SEL_PATTERN => "PATTERN",-- Select pattern value between the "PATTERN" value or the value on-- the "C" portUSE_DPORT => FALSE,-- Select D port usage, TRUE or FALSEUSE_MULT => "MULTIPLY",-- Select multiplier usage, "MULTIPLY", "DYNAMIC", or "NONE" (no-- multiplier)USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect, "PATDET", "NO_PATDET"USE_SIMD => "ONE48"-- SIMD selection, "ONE48", "TWO24", "FOUR12")port map (-- Cascade: 30-bit (each) Cascade PortsACOUT => ACOUT,-- 30-bit A port cascade outputBCOUT => BCOUT,-- 18-bit B port cascade outputCARRYCASCOUT => CARRYCASCOUT, -- 1-bit cascade carry outputMULTSIGNOUT => MULTSIGNOUT, -- 1-bit multiplier sign cascade outputPCOUT => PCOUT,-- 48-bit cascade outputVirtex-6 Libraries Guide for HDL Designs126 www.xilinx.com UG623 (v 11.4) December 2, 2009