Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 2: About UnimacrosAttribute Type Allowed Values Default DescriptionDO_REG Integer 0, 1 0 A value of 1 enables to the outputregisters to the RAM enabling quickerclock-to-out from the RAM at theexpense of an added clock cycle ofread latency. A value of 0 allows aread in one clock cycle but will haveslower clock to out timing.INIT Hexadecimal Any 72-Bit Value All zeros Specifies the initial value on theoutput after configuration.READ_WIDTH,WRITE_WIDTHInteger 1-72 36 Specifies size of DI/DO bus.READ_WIDTH and WRITE_WIDTHmust be equal.INIT_FILE String 0 bit string “NONE” Name of the file containing initialvalues.SIM_COLLISION_CHECKString“ALL,”"WARNING_ONLY","GENERATE_X_ONLY","NONE”“ALL”Allows modification of the simulationbehavior if a memory collision occurs.The output is affected as follows:• "ALL" - Warning producedand affected outputs/memorylocation go unknown (X).• "WARNING_ONLY" - Warningproduced and affectedoutputs/memory retain lastvalue.• "GENERATE_X_ONLY" - Nowarning. However, affectedoutputs/memory go unknown(X).• "NONE" - No warning andaffected outputs/memory retainlast value.Note Setting this to a value otherthan "ALL" can allow problems inthe design go unnoticed duringsimulation. Care should be takenwhen changing the value of thisattribute. Please see the Synthesisand Simulation Design Guide for moreinformation.SIM_MODE String "SAFE" or "FAST" . "SAFE" This is a simulation only attribute. Itwill direct the simulation model torun in performance-oriented modewhen set to "FAST." Please see theSynthesis and Simulation Design Guidefor more information.SRVAL Hexadecimal Any 72-Bit Value All zeroes Specifies the output value of on theDO port upon the assertion of thesynchronous reset (RST) signal.INIT_00 toINIT_7FINITP_00 toINITP_0FHexadecimal Any 256-Bit Value All zeroes Allows specification of the initialcontents of the 16kb or 32kb datamemory array.Hexadecimal Any 256-Bit Value All zeroes Allows specification of the initialcontents of the 2kb or 4kb parity datamemory array.Virtex-6 Libraries Guide for HDL Designs20 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 2: About UnimacrosVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- BRAM_SDP_MACRO: Simple Dual Port RAM-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2BRAM_SDP_MACRO_inst : BRAM_SDP_MACROgeneric map (BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"DEVICE => "VIRTEX5" -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"WRITE_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")READ_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")DO_REG => 0, -- Optional output register (0 or 1)INIT_FILE => "NONE",SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",-- "GENERATE_X_ONLY" or "NONE"SIM_MODE => "SAFE", -- Simulation: "SAFE" vs "FAST",-- see "Synthesis and Simulation Design Guide" for detailsSRVAL => X"000000000000000000", -- Set/Reset value for port outputINIT => X"000000000000000000", -- Initial values on output port-- The following INIT_xx declarations specify the initial contents of the RAMINIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 21
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Page 3 and 4: Table of ContentsXilinx Trademarks
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