Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)// Spartan-3/3E/3A/6// Xilinx HDL Libraries Guide, version 11.2BUFGMUX_1 BUFGMUX_1_inst (.O(O), // Clock MUX output.I0(I0), // Clock0 input.I1(I1), // Clock1 input.S(S) // Clock select input);// End of BUFGMUX_1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 97