Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsMMCM_BASEConvenience Primitive: Mixed signal block designed to support clock network deskew, frequencysynthesis, and jitter reduction.IntroductionThis component is a mixed signal block designed to support clock network deskew, frequency synthesis,and jitter reduction. The seven "O" counters can be independently programmed which means O0 could beprogrammed to do a divide by 2 while O1 is programmed to do a divide by 3. The only constraint is that theVCO operating frequency must be the same for all the output counters since a single VCO drives all the counters.The CLKFBOUT and CLKFBOUTB pins can be used to drive logic but it must be equal to the CLKin frequency.Port DescriptionsPort Type Width FunctionCLKFBIN Input 1 Feedback clock input.CLKFBOUT Output 1 Dedicated MMCM feedback output.CLKFBOUTB Output 1 Inverted MMCM feedback clock output.CLKIN1 Input 1 General clock input.CLKOUT[0:6] Output 7, 1–bit User configurable clock outputs (0 through 6) that can be dividedversions of the VCO phase outputs (user controllable) from 1(bypassed) to 128. The output clocks are phase aligned to eachother (unless phase shifted) and aligned to the input clock with aproper feedback configuration.CLKOUT[0:3]B Output 4, 1–bit Inverted CLKOUT[0:3].LOCKED Output 1 An output from the MMCM that indicates when the MMCMhas achieved phase alignment within a predefined window andfrequency matching within a predefined PPM range. The MMCMVirtex-6 Libraries Guide for HDL Designs224 www.xilinx.com UG623 (v 11.4) December 2, 2009