Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsOSERDESE1Primitive: Dedicated IOB Output SerializerIntroductionUse this primitive to easily implement a source synchronous interface. This device helps you by saving logicresources that would otherwise be implemented in the FPGA fabric. It also avoids additional timing complexitiesthat you might encounter when you are designing circuitry in the FPGA fabric. This element contains multipleclock inputs to accommodate various applications, and will work in conjunction with the SelectIO featuresof Xilinx® FPGAs.Port DescriptionsPort Type Width FunctionCLK Input 1 High Speed Clock Input – Use this clock input to drive theparallel-to-serial converters. The possible source for the CLK portis from one of the following clock resources:• Ten global clock lines in a clock region• Four regional clock lines• Four clock capable I/Os (within adjacent clock region)• Fabric (through bypass)CLKB Input 1 High speed clock input.Virtex-6 Libraries Guide for HDL Designs250 www.xilinx.com UG623 (v 11.4) December 2, 2009