Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- MUXF7_L: CLB MUX to tie two MUXF6’s together with local output-- For use with all FPGAs-- Xilinx HDL Libraries Guide, version 11.2MUXF7_L_inst : MUXF7_Lport map (LO => LO, -- Output of MUX to local routingI0 => I0, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)I1 => I1, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)S => S -- Input select to MUX);-- End of MUXF7_L_inst instantiationVerilog Instantiation Template// MUXF7_L: CLB MUX to tie two LUT6’s or MUXF6’s together with local output// For use with all FPGAs// Xilinx HDL Libraries Guide, version 11.2MUXF7_L MUXF7_L_inst (.LO(LO), // Output of MUX to local routing.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin).I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin).S(S) // Input select to MUX);// End of MUXF7_L_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs234 www.xilinx.com UG623 (v 11.4) December 2, 2009