Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 3: Functional CategoriesClock ComponentsDesign ElementBUFGBUFGCEBUFGCTRLBUFGMUX_CTRLBUFHBUFHCEBUFIOBUFIODQSBUFRIBUFDSIBUFDS_GTHE1IBUFDS_GTXE1MMCM_ADVDescriptionConvenience Primitive: Global Clock BufferConvenience Primitive: Global Clock Buffer with Clock EnablePrimitive: Global Clock MUX BufferConvenience Primitive: 2-to-1 Global Clock MUX BufferConvenience Primitive: Clock buffer for a single clocking regionPrimitive: Clock buffer for a single clocking region with clock enablePrimitive: Local Clock Buffer for I/OPrimitive: Differential Clock Input for Transceiver Reference ClocksPrimitive: Regional Clock Buffer for I/O and Logic ResourcesPrimitive: Differential Signaling Input BufferPrimitive: Differential Clock Input for the GTH Transceiver Reference ClocksPrimitive: Differential Clock Input for the Transceiver Reference ClocksPrimitive: MMCM is a mixed signal block designed to support clock network deskew,frequency synthesis, and jitter reduction.Config/BSCAN ComponentsDesign ElementBSCAN_VIRTEX6CAPTURE_VIRTEX6DNA_PORTEFUSE_USRFRAME_ECC_VIRTEX6ICAP_VIRTEX6STARTUP_VIRTEX6USR_ACCESS_VIRTEX6DescriptionPrimitive: Virtex®-6 JTAG Boundary-Scan Logic Access CircuitPrimitive: Virtex®-6 Readback Register Capture ControlPrimitive: Device DNA Data Access PortPrimitive: 32-bit non-volatile design IDPrimitive: Virtex®-6 Configuration Frame Error Detection and Correction CircuitryPrimitive: Internal Configuration Access PortPrimitive: Virtex®-6 Configuration Start-Up Sequence InterfacePrimitive: Virtex-6 User Access RegisterVirtex-6 Libraries Guide for HDL Designs76 www.xilinx.com UG623 (v 11.4) December 2, 2009