Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsOBUFDSPrimitive: Differential Signaling Output BufferIntroductionThis design element is a single output buffer that supports low-voltage, differential signaling (1.8 v CMOS).OBUFDS isolates the internal circuit and provides drive current for signals leaving the chip. Its output isrepresented as two distinct ports (O and OB), one deemed the "master" and the other the "slave." The master andthe slave are opposite phases of the same logical signal (for example, MYNET and MYNETB).Logic TableInputsOutputsI O OB0 0 11 1 0Port DescriptionsPort Direction Width FunctionO Output 1 Diff_p output (connect directly to top level port)OB Output 1 Diff_n output (connect directly to top level port)I Input 1 Buffer inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 243