Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsKEEPERPrimitive: KEEPER SymbolIntroductionThe design element is a weak keeper element that retains the value of the net connected to its bidirectional O pin.For example, if a logic 1 is being driven onto the net, KEEPER drives a weak/resistive 1 onto the net. If the netdriver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the net.Port DescriptionsName Direction Width FunctionO Output 1-Bit Keeper outputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- KEEPER: I/O Buffer Weak Keeper-- All FPGA, CoolRunner-II-- Xilinx HDL Libraries Guide, version 11.2KEEPER_inst : KEEPERport map (O => O -- Keeper output (connect directly to top-level port));-- End of KEEPER_inst instantiationVerilog Instantiation Template// KEEPER: I/O Buffer Weak Keeper// All FPGA, CoolRunner-II// Xilinx HDL Libraries Guide, version 11.2KEEPER KEEPER_inst (.O(O) // Keeper output (connect directly to top-level port));// End of KEEPER_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 185