Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsICAP_VIRTEX6Primitive: Internal Configuration Access PortIntroductionThis design element gives you access to the configuration functions of the FPGA from the FPGA fabric. Usingthis component, commands and data can be written to and read from the configuration logic of the FPGA array.Since the improper use of this function can have a negative effect on the functionality and reliability of the FPGA,you should not use this element unless you are very familiar with its capabilities.Port DescriptionsPort Type Width FunctionBUSY Output 1 Busy/Ready output.CLK Input 1 Clock Input.CSB Input 1 Active-Low ICAP Enable.I[31:0] Input 32 Configuration data input bus.O[31:0] Output 32 Configuration data output bus.RDWRB Input 1 Read/Write Select.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionICAP_WIDTH String “X8”, “X16”,“X32”“X8”Specifies the input and output data widthto be used with the ICAP_VIRTEX6.Virtex-6 Libraries Guide for HDL Designs162 www.xilinx.com UG623 (v 11.4) December 2, 2009