Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// EFUSE_USR: 32-bit non-volatile design ID// Virtex-6// Xilinx HDL Language Template, version 11.1EFUSE_USR #(.SIM_EFUSE_VALUE(32’h00000000))EFUSE_USR_inst (.EFUSEUSR(EFUSEUSR));// End of EFUSE_USR_inst instantiation// Causes simulation model to drive a static value onto these pins after// INIT goes high.// 32-bit User E-Fuse register valueFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 131