Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsCARRY4Primitive: Fast Carry Logic with Look AheadIntroductionThis circuit design represents the fast carry logic for a slice. The carry chain consists of a series of four MUXesand four XORs that connect to the other logic (LUTs) in the slice via dedicated routes to form more complexfunctions. The fast carry logic is useful for building arithmetic functions like adders, counters, subtractors andadd/subs, as well as such other logic functions as wide comparators, address decoders, and some logic gates(specifically, AND and OR).Port DescriptionsPort Direction Width FunctionO Output 4 Carry chain XOR general data outCO Output 4 Carry-out of each stage of the carry chainDI Input 4 Carry-MUX data inputS Input 4 Carry-MUX select lineCYINIT Input 1 Carry-in initialization inputCI Input 1 Carry cascade inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL Designs112 www.xilinx.com UG623 (v 11.4) December 2, 2009