Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design ElementsDesign Entry MethodTo instantiate this component, use the Embedded Development Kit (EDK) or an associated core containing thecomponent. Xilinx does not recommend direct instantiation of this component.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs318 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 4: About Design ElementsUSR_ACCESS_VIRTEX6Primitive: Virtex-6 User Access RegisterIntroductionThis design element enables access to a 32-bit register within the configuration logic. You will thus be able toread the data from the bitstream. One use for this component is to allow data stored in bitstream storage sourceto be accessed by the FPGA design after configuration.Port DescriptionsPort Type Width FunctionCFGCLK Output 1 Configuration ClockDATA[31:0] Output 32 Configuration Output DataDATAVALID Output 1 Active high DATA port contains valid dataDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- USR_ACCESS_VIRTEX6: Virtex-6 User Access Register-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2USR_ACCESS_VIRTEX6_inst : USR_ACCESS_VIRTEX6generic map ()port map (CFGCLK => CFGCLK, -- 1-bit Configuration ClockDATA => DATA,-- 32-bit Configuration Output DataDATAVALID => DATAVALID -- 1-bit Active high DATA port contains valid data);-- End of USR_ACCESS_VIRTEX6_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 319
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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