Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsBUFGMUX_CTRLConvenience Primitive: 2-to-1 Global Clock MUX BufferIntroductionThis design element is a global clock buffer with two clock inputs, one clock output, and a select line used tocleanly select between one of two clocks driving the global clocking resource. This component is based onBUFGCTRL, with some pins connected to logic High or Low. This element uses the S pin as the select pin for the2-to-1 MUX. S can switch anytime without causing a glitch on the output clock of the buffer.Port DescriptionsPort Direction Width FunctionO Output 1 bit Clock OutputI0 Input 1 bit One of two Clock InputsI1 Input 1 bit One of two Clock InputsS Input 1 bit Select for I0 (S=0) or I1 (S=1)Clock OutputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFGMUX_CTRL: Global Clock Buffer 2-to-1 MUX-- Virtex-5/6-- Xilinx HDL Libraries Guide, version 11.2BUFGMUX_CTRL_inst : BUFGMUX_CTRLport map (O => O, -- Clock MUX outputI0 => I0, -- Clock0 inputI1 => I1, -- Clock1 inputS => S -- Clock select input);-- End of BUFGMUX_CTRL_inst instantiationVirtex-6 Libraries Guide for HDL Designs98 www.xilinx.com UG623 (v 11.4) December 2, 2009