Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsQ1 => Q1,Q2 => Q2,Q3 => Q3,Q4 => Q4,Q5 => Q5,Q6 => Q6,-- SHIFTOUT1/SHIFTOUT2: 1-bit (each) If ISERDES_MODE="MASTER" and two ISERDES_NODELAY are to be cascaded,-- connect to the slave ISERDES_NODELAY IDATASHIFTIN1/2 inputs.SHIFTOUT1 => SHIFTOUT1,SHIFTOUT2 => SHIFTOUT2,BITSLIP => BITSLIP,-- 1-bit Input data bitslip function enable.CE1 => CE1,-- 1-bit Input data register clock enables.CE2 => CE2,-- 1-bit DITTOCLK => CLK,CLKB => CLKB,-- 1-bit Primary clock input pin used.-- 1-bit Secondary clock input. If using in single clock DDR mode-- (DATA_RATE="DDR"), invert the clock connected to the CLK pin and connect-- to the CLKB pin. If using in dual clock mode DDR mode, connect a unique,-- phase shifted clock to the CLKB pin. If using in single data-rate mode-- (DATA_RATE="SDR"), leave this pin unconnected or connect to ground.CLKDIV => CLKDIV,D => D,-- 1-bit Divided clock to be used for parallelized data.-- 1-bit Input data to be connected directly to the top-level input or I/O-- port of the design or to an IODELAY component if additional input delay-- control is desired.);DDLY => DDLY,DYNCLKDIVSEL => DYNCLKDIVSEL, -- 1-bit Dynamically select CLKDIV or CLKDIV_B (via an optional inversion).DYNCLKSEL => DYNCLKSEL, -- 1-bit Dynamically select CLK or CLK_B (via an optional inversion).OCLK => OCLK,-- 1-bit High speed output clock typically used for memory interfaces.OFB => OFB,-- 1-bit Feedback Path from the OLOGIC/OSERDES Output (w/ or w/o ODELAY).RST => RST,-- 1-bit Active high asynchronous reset signal for the registers of the-- SERDES.-- SHIFTIN1/SHIFTIN2: 1-bit (each) If ISERDES_MODE="SLAVE" connect to the master ISERDES_NODELAY-- IDATASHIFTOUT1/2 outputs. This pin must be grounded.SHIFTIN1 => SHIFTIN1,SHIFTIN2 => SHIFTIN2-- End of ISERDESE1_inst instantiationVirtex-6 Libraries Guide for HDL Designs182 www.xilinx.com UG623 (v 11.4) December 2, 2009