Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsOR2LPrimitive: Two input OR gate implemented in place of a Slice LatchIntroductionThis element allows the specification of a configurable Slice Latch to take the function of a two input OR gate (seeLogic Table). The use of this element can reduce logic levels and increase logic density of the part by trading offregister/latch resources for logic. Xilinx suggests caution when using this component as it can affect registerpacking and density since specifying one or more e AND2B1L or OR2L components in a Slice disallows the useof the remaining registers and latches.Logic TableInputsOutputsDI SRI O0 0 00 1 11 0 11 1 1Port DescriptionsPort Type Width FunctionO Output 1 Output of the OR gate.DI Input 1 Active high input that is generally connected to sourcing LUT locatedin the same Slice.SRI Input 1 Active low input that is generally source from outside of the Slice.Note To allow more than one AND2B1L or OR2B1L to be packed intoa single Slice, a common signal must be connected to this input.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 249