Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort DescriptionsPort Type Width FunctionCAPTURE Output 1 Active upon the loading of the USER instruction. Asserts High whenthe JTAG TAP controller is in the CAPTURE-DR state.DRCK Output 1 A mirror of the TCK input pin to the FPGA when the JTAG USERinstruction assigned by JTAG_CHAIN is loaded and the JTAG TAPcontroller is in the SHIFT-DR state or in the CAPTURE-DR state.RESET Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in theTEST-LOGIC-RESET state.RUNTEST Output 1 Indicates that JTAG is in Run Test/Idle state. Asserts high when JTAGTAP controller is in RTI stateSEL Output 1 Indicates when the USER instruction has been loaded into the JTAGInstruction Register. Becomes active in the UPDATE-IR state, and staysactive until a new instruction is loaded.SHIFT Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in the SHIFT-DR state.TCK Output 1 A mirror of the value of the TCK input pin to the FPGA.TDI Output 1 A mirror of the TDI pin.TMS Output 1 A mirror of the TMS pin.UPDATE Output 1 Active upon the loading of the USER instruction. It asserts High whenthe JTAG TAP controller is in the UPDATE-DR state.TDO Input 1 Active upon the loading of the USER instruction. External JTAG TDOpin will reflect data input to the macro’s TDO1 pin.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionDISABLE_JTAG Boolean TRUE, FALSE FALSE Attached to BSCAN_VIRTEX6 instance 1.JTAG_CHAIN Integer 1, 2, 3, 4 1 Sets the JTAG USER instruction number that this instanceof the element will handle.Virtex-6 Libraries Guide for HDL Designs84 www.xilinx.com UG623 (v 11.4) December 2, 2009