Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsIBUFDS_GTXE1Primitive: Differential Clock Input for the Transceiver Reference ClocksIntroductionThis component is the differential clock input for the transceiver reference clocks. It can also drive otherclock resources such as BUFG/MMCM as well as the reference clock inputs of the GT. It typically connectsto the MGTREFCLKRX/TX pins of the 4 GTXE1 in the quad associated with the IBUFDS_GTXE1, to theNORTHREFCLKRX/TX of the 4 GTXE1 in the quad above, or to the SOUTHREFCLKRX/TX pins of the 4 GTXE1in the quad below.There are multiple destination pins in Virtex®-6 devices that the IBUFDS_GTXE1 element could connect to. Ifone reference clock on the GT is connected, SW has full control and can route and connect to the GT on any of thepins based on the most optimal route. If multiple clocks are connected to the GT then SW will route each IBUFDSto the indicated pin on the GT. So the O pin on the IBUFDS_GTXE1 connects to either the MGTREFCLKRX/TX orthe NORTH/SOUTHREFCLKRX/TX pins on the GT.Note The RX and TX MUXes can be chosen independently, but the routes are shared on physical silicon.Design Entry MethodTo instantiate this component, use the RocketIO wizard or an associated core containing the component. Xilinxdoes not recommend direct instantiation of this component.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 157