Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design Elements.DATA_WIDTH(4),// If DATA_RATE_OQ = DDR, value is limited to 4, 6, 8, or 10. If DATA_RATE_OQ// = SDR, value is limited to 2, 3, 4, 5, 6, 7, or 8..DDR3_DATA(1),// For DDR3, if the I/O is a DQ or DQS pin, set to 1. If control, address,// clock, etc. set to 0..INIT_OQ(1’b0),// Defines the initial value of OQ output..INIT_TQ(1’b0),// Defines the initial value of TQ output..INTERFACE_TYPE("DEFAULT"), // To bypass DDR3 circuitry.ODELAY_USED(0),// BUFO drives IODELAY for write leveling or BUFO alignment..SERDES_MODE("MASTER"), // Defines whether the OSERDES module is a master or slave when width// expansion is used..SRVAL_OQ(1’b0),// Defines the value of OQ output when reset is invoked..SRVAL_TQ(1’b0),// Defines the value of TQ output when reset is invoked..TRISTATE_WIDTH(4)// If DATA_RATE_TQ = DDR, DATA_WIDTH = 4, and DATA_RATE_OQ = DDR, value is// limited to 1 or 4. For all other settings of DATA_RATE_TQ, DATA_WIDTH, and// DATA_RATE_OQ, value is limited to 1.)OSERDESE1_inst (.OCBEXTEND(OCBEXTEND),.OFB(OFB),// 1-bit Feedback path for Data Output.OQ(OQ),// 1-bit Data Path Output// SHIFTOUT1/SHIFTOUT2: 1-bit (each) Carry Out for data input expansion. Connect to SHIFTIN1/2 ofter..SHIFTOUT1(SHIFTOUT1),.SHIFTOUT2(SHIFTOUT2),.TFB(TFB),);.TQ(TQ),.CLK(CLK),// 1-bit 3-State Path Output// 1-bit High Speed Clock Input - This clock input is used to drive the// parallel-to-serial converters. The possible source for the CLK port is// from one of the following clock resources: - Ten global clock lines in a// clock region - Four regional clock lines - Four clock capable I/Os// (within adjacent clock region) - Fabric (through bypass)..CLKDIV(CLKDIV),// 1-bit Divided High Speed Clock Input.CLKPERF(CLKPERF),// 1-bit Input for performance path from PLL..CLKPERFDELAY(CLKPERFDELAY), // 1-bit Delayed version of BUFO from IODELAY// D1 - D6: 1-bit (each) 1-bit parallel Data Input.D1(D1),.D2(D2),.D3(D3),.D4(D4),.D5(D5),.D6(D6),.OCE(OCE),// 1-bit Parallel to serial converter (data) clock enable.ODV(ODV),// 1-bit Used for DDR3. Set to 1 if the ODELAY values exceeds 180 degrees of// the clock period..RST(RST),// SHIFTIN1/SHIFTIN2: 1-bit (each) 1-bit Data Input Expansion.SHIFTIN1(SHIFTIN1),.SHIFTIN2(SHIFTIN2),// T1 - T4: 1-bit (each) Parallel 3-State Inputs.T1(T1),.T2(T2),.T3(T3),.T4(T4),.TCE(TCE),.WC(WC)// End of OSERDESE1_inst instantiation// 1-bit Parallel to serial converter (3-state) clock enable// 1-bit Used for DDR3. Resets FIFO counters and turns IODELAY from IDELAY// to ODELAY.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs254 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 4: About Design ElementsPCIE_2_0Primitive: PCI Express version 2.0 Compliant.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 255
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Virtex-6 Libraries Guide forHDL Des
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Table of ContentsXilinx Trademarks
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