Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosADDSUB_MACROMacro: Adder/SubtractorIntroductionThe ADDSUB _MACRO simplifies the instantiation of the DSP48 block when used as a simple adder/subtractor.It features parameterizable input and output widths and latency that ease the integration of the DSP48 block intoHDL.Port DescriptionName Direction Width (Bits) FunctionOutput PortsCARRYOUT Output 1 Carry OutRESULT Output Variable, see WIDTH attrribute. Data output bus addressed by RDADDR.Input PortsADDSUB Input 1 When high, RESULT is an addition. When low,RESULT is a subtraction.A Input Variable, see WIDTH attribute. Data input to add/sub.B Input Variable, see WIDTH_B attribute. Data input to add/subCE Input 1 Clock EnableCARRYIN Input 1 Carry InCLK Input 1 ClockRST Input 1 Synchronous ResetDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 57