Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- BUFR: Regional Clock Buffer for I/O and Logic Resources-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2BUFR_inst : BUFRgeneric map (BUFR_DIVIDE => "BYPASS", -- Defines whether the output clock is a divided version of input clock.SIM_DEVICE => "VIRTEX4")port map (O => O,-- 1-bit Clock output port. This port drives the clock tracks in the clock region of the BUFR-- and the two adjacent clock regions. This port drives FPGA fabric, and IOBs.CE => CE, -- 1-bit Clock enable port. When asserted Low, this port disables the output clock at port O.-- When asserted High, this port resets the counter used to produce the divided clock output.CLR => CLR, -- 1-bit Counter reset for divided clock output. When asserted High, this port resets the-- counter used to produce the divided clock output.I => I-- 1-bit Clock input port. This port is the clock source port for BUFR. It can be driven by-- BUFIO output or local interconnect.);-- End of BUFR_inst instantiationVerilog Instantiation Template// BUFR: Regional Clock Buffer /w Enable, Clear and Division Capabilities// Virtex-4/5, Virtex-6// Xilinx HDL Libraries Guide, version 11.2BUFR #(.BUFR_DIVIDE("BYPASS"), // "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8".SIM_DEVICE("VIRTEX4") // Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6") BUFR_inst (.O(O), // Clock buffer output.CE(CE), // Clock enable input.CLR(CLR), // Clock buffer reset input.I(I) // Clock buffer input);// End of BUFR_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 109