Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsFDREPrimitive: D Flip-Flop with Clock Enable and Synchronous ResetIntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputsand data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q)output Low on the Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when Ris Low and CE is High during the Low-to-High clock transition.This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsR CE D C Q1 X X ↑ 00 0 X X No Change0 1 D ↑ DDesign Entry MethodThis design element is only for use in schematics.Available AttributesAttribute Type Allowed Values Default DescriptionINIT Binary 0 0 Sets the initial value of Q output after configuration.For Spartan®-6 the INIT value should always matchthe polarity of the set or reset. In the case of FDRE, theINIT should be 0. If set to 1, extra logic is inserted.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 135