Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// FIFO18E1: 18KB FIFO (First In, First Out) Block RAM Memory// Virtex-6// Xilinx HDL Language Template, version 11.1FIFO18E1 #(.ALMOST_EMPTY_OFFSET(13’h0080), // Sets the almost empty threshold.ALMOST_FULL_OFFSET(13’h0080), // Sets almost full threshold.DATA_WIDTH(4), // Sets data width to 4, 9, 18, or 36.DO_REG(1),// Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE".EN_SYN("FALSE"),// Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE").FIFO_MODE("FIFO18"),// Sets mode to FIFO18 or FIFO18_36.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to "TRUE" or "FALSE".INIT(36’h000000000),// Initial values on output port.SRVAL(36’h000000000)// Set/Reset value for output port)FIFO18E1_inst (.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag.DO(DO),// 32-bit data output.DOP(DOP),// 4-bit parity data output.EMPTY(EMPTY),// 1-bit empty output flag.FULL(FULL),// 1-bit full output flag// WRCOUNT, RDCOUNT: 12-bit (each) FIFO write/read pointer..RDCOUNT(RDCOUNT),// 12-bit read count output.WRCOUNT(WRCOUNT),// 12-bit write count output// WRERR, RDERR: 1-bit (each) WRERR indicates that a write occurred while the FIFO was full and RDERR// indicates that a read occurred while the FIFO was empty.RDERR(RDERR),// 1-bit read error output.WRERR(WRERR),// 1-bit write error.DI(DI),// 32-bit data input.DIP(DIP),// 4-bit parity input.RDEN(RDEN),// 1-bit read enable input.REGCE(REGCE),// 1-bit clock enable input.RST(RST),// 1-bit reset input.RSTREG(RSTREG),// 1-bit output register set/reset// WRCLK, RDCLK: 1-bit (each) FIFO read and write clocks (positive edgeggered)..RDCLK(RDCLK),// 1-bit read clock input.WRCLK(WRCLK),// 1-bit write clock input.WREN(WREN)// 1-bit write enable input);// End of FIFO18E1_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs140 www.xilinx.com UG623 (v 11.4) December 2, 2009