Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort DescriptionName Direction Width FunctionL0 Output 1 6/5-LUT output for internal CLB connectionI0, I1, I2, I3, I4 Input 1 LUT inputsDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 32-Bit Value All zeros Specifies the logic value for the look-uptables.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- LUT5: 5-input Look-Up Table with general output-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2LUT5_inst : LUT5generic map (INIT => X"00000000") -- Specify LUT Contentsport map (O => O, -- LUT general outputI0 => I0, -- LUT inputI1 => I1, -- LUT inputI2 => I2, -- LUT inputI3 => I3, -- LUT inputI4 => I4 -- LUT input);-- End of LUT5_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 199