Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IOBUFDS: Differential Bi-directional Buffer-- Spartan-3/3E/3A-- Xilinx HDL Libraries Guide, version 11.2IOBUFDS_inst : IOBUFDSgeneric map (IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,-- "0"-"12" (Spartan-3E)-- "0"-"16" (Spartan-3A)IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,-- "AUTO", "0"-"6" (Spartan-3E)-- "AUTO", "0"-"8" (Spartan-3A)IOSTANDARD => "DEFAULT")port map (O => O, -- Buffer outputIO => IO, -- Diff_p inout (connect directly to top-level port)IOB => IOB, -- Diff_n inout (connect directly to top-level port)I => I, -- Buffer inputT => T -- 3-state enable input, high=input, low=output);-- End of IOBUFDS_inst instantiationVerilog Instantiation Template// IOBUFDS: Differential Bi-directional Buffer// Virtex-4/5, Spartan-3/3E/3A// Xilinx HDL Libraries Guide, version 11.2IOBUFDS #(.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer,// "0"-"12" (Spartan-3E only), "0"-"16" (Spartan-3A only).IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,// "AUTO", "0"-"6" (Spartan-3E only), "0"-"8" (Spartan-3A only).IOSTANDARD("DEFAULT") // Specify the I/O standard) IOBUFDS_inst (.O(O), // Buffer output.IO(IO), // Diff_p inout (connect directly to top-level port).IOB(IOB), // Diff_n inout (connect directly to top-level port).I(I), // Buffer input.T(T) // 3-state enable input, high=input, low=output);// End of IOBUFDS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs174 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 4: About Design ElementsIODELAYE1Primitive: Input and Output Fixed or Variable Delay ElementIntroductionThis design element can be used to provide a fixed delay or an adjustable delay to the input path and a fixeddelay for the output path of the Virtex®-6 FPGA. This delay can be useful for data alignment of incoming oroutgoing data to/from the chip, as well as allowing for the tracking of data alignment over process, temperature,and voltage (PVT). When used in variable mode, the input path can be adjusted for increasing and decreasingamounts of delay. The output delay path is only available in a fixed delay. The IODELAY can also be used to addadditional static or variable delay to an internal path (within the FPGA fabric). However, when IODELAY is usedthat way, this device is no longer available to the associated I/O for input or output path delays.Port DescriptionsPort Type Width FunctionC Input 1 Clock input (Must be connected for variable mode).CE Input 1 Active high enable increment/decrement function.CINVCTRL Input 1 Dynamically inverts the Clock (C) polarity.CLKIN Input 1 Clock Access into the IODELAY (from the IO CLKMUX).CNTVALUEIN[4:0] Input 5 Counter value from fabric for loadable counter application.CNTVALUEOUT[4:0] Output 5 Counter value going to fabric for monitoring purpose.DATAIN Input 1 Data input for the internal datapath delay. When DATAIN is used,IDATAIN and ODATAIN must be tied to a logic zero (ground).DATAOUT Output 1 Delayed data output from input port (connect to input datapathlogic).IDATAIN Input 1 Data input to device from the I/O (connect directly to port, I/OBuffer). When IDATAIN is used, DATAIN must be tied to a logiczero (ground).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 175
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